The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to solder bump connections and methods for fabricating solder bump connections during back-end-of-line (BEOL) processing of semiconductor chips.
A chip or die includes integrated circuits formed by front-end-of-line (FEOL) processing and metallization levels of an interconnect structure formed by back-end-of line (BEOL) processing. Chips are then packaged and mounted on a circuit board. Solder bumps are commonly utilized to provide mechanical and electrical connections between the last or top metallization level and the circuit board. A common type of solder bump is the controlled collapse chip connection (C4) solder bump. Controlled Collapse Chip Connection (C4) processes are well known in forming solder bumps in semiconductor fabrication. During assembly of the chip and circuit board, C4 solder bumps establish physical attachment and electrical contact between an array of C4 pads on the chip and a complementary array of C4 pads on the circuit board.
Conventional solder bump connections rely on a group of metallic layers know as the Ball Limiting Metallurgy (BLM) to promote the attachment of the C4 solder bump to the chip. Among the functions of the BLM are to promote adhesion between the underlying dielectric passivation layer and the metal pad, to promote solder wetting, and to act as a solder diffusion barrier.
Improved solder bump connections and fabrication methods are needed that improve on conventional solder bump connections and methods.